In this article, we will discuss a delay analysis model that estimates the delay from a source(root) to one of the leaf nodes as the sum of the resistance in the path to the ith node multiplied by the capacitance present at the end of the branch. The Elmore delay model provides a simplistic delay analysis that avoids time-consuming numerical integration/differential equations of an RC network.
source https://www.allaboutcircuits.com/technical-articles/elmore-delay-model-transistor-sizing-vlsi-design/
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